中文摘要
降低晶片操作電壓是一個已知降低晶片功率消耗的最有效方法。因此，多電源模式(Multiple-Power-Mode)的晶片設計被廣泛應用在整個IC產業之中。然而，當多電源模式晶片的工作電壓運作在廣域電壓之下，非常大的時脈差異將會發生在不同的電源模式之間。為了降低這時脈差異，傳統的電源模式感知緩衝器必須使用到一定的數量的時脈緩衝器，因而產生較大的功率消耗。在本篇文章當中，之於廣域電壓下的晶片設計，我們提出一個新的電源模式感知緩衝器電路架構。此電路架構由兩個串接的電源模式感知緩衝器組合而成，在第一層級的電源模式感知緩衝器，我們供應較低電壓來概略調整時脈差異；在第二層級的電源模式感知緩衝器，我們供應較高電壓來細部微調時脈差異。實驗結果顯示我們提出的新電源模式感知緩衝器電路架構的確能有效降低時脈差異，同時避免產生額外的功率消耗。
Abstract
Lowering the supply voltage is recognized as the most effective way to reduce power consumption. Therefore, multiple-power-mode designs have been widely adopted in the industry. However, in a multi-power-mode design, as the range of the supply voltage becomes wide, a large clock skew may occur among different power domains. To remove this clock skew, conventional power-mode-aware buffers (PMABs) require a large overhead on power consumption. In this paper, we propose a new PMAB architecture for wide-voltage-range multi-power-mode designs. The proposed PMAB architecture is composed of two serially-connected sub-PMABs at two different voltage levels, respectively: in the front sub-PMAB, the low voltage level is used for coarse-grained clock skew minimization; in the back sub-PMAB, the high voltage level is used for fine-grained clock skew minimization. Benchmark data show that the proposed approach can effectively eliminate the clock skew with small power consumption.
關鍵詞(Key Words)
多電源模式 (Ｍulti-power Mode)
廣域電壓 (Wide-voltage Range)
時脈差異 (Clock Skew)
時脈樹 (Clock Tree)
相關檔案: 廣域電壓之電源模式感知時脈樹設計(全文)
