中文摘要
數位存儲示波器(Digital Storage Oscilloscope ; DSO)的開發主要分為三個部分：類比電路設計，數位電路設計與軟體開發，因此將三個部分進行系統整合是一個既漫長又複雜的過程，故建立電子系統層級(Electronic System Level ; ESL)驗證平台，是一項可達到「更可靠」及「更智慧」的電路設計技術。本論文的重點在開發數位存儲示波器的流程中，導入ESL設計流程，在設計開發初期，即利用軟硬整合虛擬平台，進行軟硬體分工的系統效能探索、系統軟體開發等。甚至，更進一步利用高階設計環境，進行軟硬體開發初期的效能分析，決定應用軟體開發時的資料結構，進而達到高效率之軟硬體協同資料結構建置；本論文利用ESL環境分析數位存儲示波器系統架構，著重於資料流與時間的關係，藉由調整記憶體類型，分析硬體的平行處理行為及記憶體存取權，進而提出高速波形更新之架構，將高速的關鍵性零組件整合到客製化的關鍵ASIC上；對於量測儀器這種系統龐大且複雜產品，將可有效縮短產品的開發時程，達到「更可靠」及「更智慧」的電路設計；本論文利用ESL設計流程開發波形更新及顯示的專用晶片(ASIC)，用以符合中高階數位存儲示波器系統效能之需求，並掌握高速波形更新晶片技術。而本晶片技術額外包含高速取樣與補點技術、高速與長記憶記憶體存取技術、及數位觸發技術(Digital Trigger)…等，晶片採用TSMC 90nm製程，其波形擷取/更新率(Waveform Capture/Update Rate)高達每秒125萬次，且晶片具有LVDS 1.6Gbps介面與FPGA連接。
Abstract
The development of digital storage oscilloscope is divided into three parts: analog circuit design, digital circuit design and software development. Systems integration is a long and complex process. So, create a system verification platform is an extremely complex project. This paper focuses on the development of digital storage oscilloscope processes and combine an electronic system-level (Electronic System Level; ESL) design flow. In the early design and development, software and hardware can integrate into one virtual platform for hardware and software co-simulation. Users can use this ESL environment to do system performance exploration and system software development. Even, user can further use high-end design environment for analysis hardware and software development effectively and determines data structure. This paper uses ESL environment to analyze the digital storage oscilloscope system architecture and focus on data flow versus time. By analyzing and adjusting the parallel processing behavior and memory access behavior and memory type, propose high-speed waveform update rate architecture. Use customized ASIC to implement the high speed key components. Use customized ASIC will be to reduce the development time for measuring instruments and achieve more reliable and more intelligent circuit design. In this paper, we develop waveform update and display customized chip to meet the needs of high-end digital storage oscilloscope system performance and master high-speed waveform update chip technology. The chip contains a high-speed sampling technique、extra point fill technology、high-speed memory access、long memory technology and digital trigger technology. This chip use TSMC 90nm manufacturing process and the chip is up to 1.25 million waveform capture/update rate. It is also with LVDS 1.6Gbps interface, which is used to connect FPGA easier.
關鍵詞(Key Words)
電子系統層級(Electronic System Level ; ESL)
數位存儲示波器(Digital Storage Oscilloscope ; DSO)
波形更新晶片(Fast Frame Update Rate Circuit)
相關檔案: 基於電子系統層級設計流程進行高速波形更新晶片設計(全文)
